1. Technical Field
This disclosure relates generally to electronic circuits, and in particular, to circuits for wireless communication.
2. Description of the Related Art
In a radio receiver, selectivity is an important specification for systems employing multiple frequency channels (e.g., the 2.4 GHz Industrial, Scientific, and Medical (ISM) band). Selectivity is the ability to receive the desired channel frequency (desired, Fd) in the presence of other signals having undesired channel frequencies (undesired, Fu). This is analogous to a person listening to a conversation taking place across the room in a room-full of conversations.
One method of rejecting the Fu (and only “listening” to Fd) is accomplished with a Band-Pass Filter (BPF), which only allows Fd to pass through it for further processing by the radio circuitry. It can be very difficult and/or expensive to design a BPF at the incoming RF frequency (in this case, 2.4 GHz).
For example, if the channel frequencies are spaced 1 MHz apart, the BPF bandwidth would have to be approximately 1 MHz to reject the other channels. This would require a Q of 2,400 for a Radio Frequency (RF) BPF (2.4 GHz/1 MHz) but only a Q of 10 for a BPF with an Intermediate Frequency (IF) of 10 MHz (10 MHz/1 MHz). It can be difficult and expensive to design an RF BPF with a Q of 2,400, hence the need to create an IF and perform the filtering at the IF.
In many low IF transceivers, the transmitter is on the same frequency as the Local Oscillator (LO), but the receiver is not. The receiver LO must be moved by a frequency increment equal to the IF frequency, when compared to the transmitter LO. Assuming that there is only one local oscillator, this requires that the Phase-Locked Loop (PLL) of the frequency synthesizer be re-locked.
A conventional technique in radio design is to use a Mixer to perform frequency translation (i.e., multiplying two frequencies (F1, F2) to obtain the sum and difference frequencies (Fout)=M*F1+/−N*F2 (where M or N=1, 2, 3, . . .)=F1+F2, F1−F2, 2*F1+/−F2, 2*F2+/−F1, 3*F1+/−2*F2, etc.).
A simple case is where a user wants to convert an incoming RF signal (e.g., FRF=2.402 GHz) to an IF (e.g., 1 MHz). This is accomplished by mixing FRF with a local oscillator frequency (LO) of FLO=2.401 GHz. Note that FRF is 1 MHz “above” FLO. Now observe that FRF=2.400 GHz (1 MHz “below” the LO) also produces a difference frequency of 1 MHz (actually, −1 MHz, which is described as +1 MHz with a spectrum inversion). Thus, 2.400 GHz is the “image” (FImage) of FRF=2.402 GHz for an FLO of 2.401 GHz and an IF of 1 MHz.
Radios employing mixers for frequency translation are susceptible to interference from their image frequency. There are conventional techniques, such as the use of image canceling mixers that can obviate this susceptibility. For an IF of 2 MHz and FLO=2.401 GHz (unchanged), FRF=2.403 GHz and FImage=2.399 GHz. Also note the roles of FRF and FImage can be reversed depending on which RF signal is the frequency one wishes to receive. Alternatively, one can use a zero IF receiver, which has no image.
An illustration of this conventional requirement to re-lock the PLL is illustrated in FIG. 1, where FIG. 1 is a block diagram illustrating a method of communication between two transceivers according to a conventional technique.
Referring to FIG. 1, the operation of the first transceiver is illustrated on the left side of the dotted line, while the operation of the second transceiver is illustrated on the right side of the dotted line. Both the first and second transceiver include only a single LO. The transmitters of the first and second transceivers will always transmit at the frequency of their corresponding LO.
Initially, the first transceiver transmits to the second transceiver (upper left corner to upper right corner of FIG. 1) at 2402 MHz. The receiver of the second transceiver is set to receive at 2402 MHz, but the LO of the second transceiver is set to 2403 MHz in order to perform the mixing operation to downconvert the received signal to 1 MHz IF.
The first transceiver expects to receive an acknowledgement from the second transceiver that the signal from the first transceiver was received. Since the first transceiver expects to receive a signal from the second transceiver at 2403 MHz, both the first and second transceivers must change the frequency of their respective LO after the first transceiver transmits to the second transceiver.
That is, the second transceiver must change the frequency of its LO from 2403 MHz to 2402 MHz to transmit to the first transceiver. Likewise, the first transceiver must change the frequency of its LO from 2402 MHz to 2403 MHz in order to perform the mixing operation to downconvert the received signal from the second transceiver to 1 MHz IF.
According to the conventional technique described above, each time that a data burst is sent there must be at least one change of LO frequency for both the first transceiver and the second transceiver. Changing the LO frequency, however, may require a significant amount of time because the PLL cannot instantly be set to the new frequency. There is always some time required for the PLL to stabilize at the new LO frequency. The re-locking of the PLL with each change of LO frequency implies some latency in the delivery of data. The additional time required to re-lock the PLL also means that the first and second transceivers must be powered for a longer amount of time for each data burst, which negatively affects current consumption and battery life.
Another conventional solution is to have two independent LOs, one LO for receiving and one LO for transmitting. However, this conventional solution requires more power consumption and chip area, which are also undesirable. Also, there is design difficulty due to possible interactions (“pulling”) between the two oscillators.
It would be desirable to have a faster PLL lock time with lower current consumption. A lower power PLL is desirable in battery powered applications and faster lock time is desirable also when you transmit/receive data in short bursts where long lower power idle times and/or PLL lock times are a significant fraction of the time it takes to transmit/receive a data packet.
Embodiments of the invention address these and other disadvantages of the related art.